This application relates to ferroelectric thin films which are used in nonvolatile memories and specifically to a metal-ferroelectric-metal-silicon semi-conductor, also referred to herein as a ferroelectric memory (FEM) cell. Known ferroelectric random access memories (FRAM) are constructed with one transistor (1T) and one capacitor (1C). The capacitor is generally made by sandwiching a thin ferroelectric film between two conductive electrodes, which electrodes are usually made of platinum. The circuit configuration and the read/write sequence of this type of memory are similar to that of conventional dynamic random access memories (DRAM), except that no data refreshing is necessary in a FRAM. Known FRAMs have a fatigue problem that has been observed in the ferroelectric capacitor, which is one of the major obstacles that limit the viable commercial use of such memories. The fatigue is the result of a decrease in the switchable polarization (stored nonvolatile charge) that occurs with an increased number of switching cycles. As used in this case, xe2x80x9cswitching cyclesxe2x80x9d refers to the sum of reading and writing pulses in the memory.
Another known use of ferroelectric thin films in memory applications is to form a ferroelectric-gate-controlled field effect transistor (FET) by depositing the ferroelectric thin film directly onto the gate area of the FET. Such ferroelectric-gate controlled devices have been known for some time and include devices known as metal-ferroelectric-silicon (MFS) FETs. FRAMs incorporating the MFS FET structure have two major advantages over the transistor-capacitor configuration: (1) The MFS FET occupies less surface area, and (2) provides a non-destructive readout (NDR). The latter feature enables a MFS FET device to be read thousands of times without switching the ferroelectric polarization. Fatigue, therefore, is not a significant concern when using MFS FET devices. Various forms of MFS FET structures may be constructed, such as metal ferroelectric insulators silicon (MFIS) FET, metal ferroelectric metal silicon (MFMS) FET, and metal ferroelectric metal oxide silicon (MFMOS) FET.
There are a number of problems that must be overcome in order to fabricate an efficient MFS FET device. The first problem is that it is difficult to form an acceptable crystalline ferroelectric thin film directly on silicon. Such structure is shown in U.S. Pat. No. 3,832,700. Additionally, it is very difficult to have a clean interface between the ferroelectric material and the silicon. Further, there is a problem retaining an adequate charge in the ferroelectric material. A FEM structure on a gate region is shown in U.S. Pat. No. 5,303,182, which emphasizes that the transfer of metal ions into the gate region is undesirable. Similar structure is shown in U.S. Pat. No. 5,416,735.
It is an object of this invention to overcome the aforementioned problems.
Another object of the invention is to provide a FEM device which provides a non-destructive readout.
Yet another object of the invention to provide a FEM device that occupies a relatively small surface area.
A further object of the invention is to provide an FEM device which requires a relatively low programming voltage.
The method of forming a semiconductor memory device on a silicon substrate includes implanting doping impurities of a first type in the silicon substrate to form a conductive channel of a first type for use as a gate region, forming a MOS capacitor on the conductive channel of the first type, depositing an FEM capacitor over the MOS capacitor, including depositing a lower metal layer, a FE layer and an upper metal layer, thereby forming a stacked gate unit, implanting doping impurities of a second type in the silicon substrate on either side of the gate region to form a conductive channel of a second type for use as a source junction region and a drain junction region, and depositing an insulating structure about the FEM gate unit.
A ferroelectric memory (FEM) cell constructed according to the invention includes a silicon substrate, a gate region located in said substrate; doped to form a conductive channel of a first type, a source junction region and a drain junction region located in the substrate on either side of the gate region, doped to form a pair of conductive channels of a second type, a MOS capacitor, including an oxide layer and an upper metal layer located over the gate junction region, wherein the MOS capacitor has a predetermined surface area, a FEM capacitor, including a lower metal layer, a FE layer and an upper metal layer; wherein the FEM capacitor is stacked on and overlays at least a portion of the MOS capacitor, thereby forming, with the MOS capacitor, a stacked gate unit, an insulating layer, having an upper surface, overlying the junction regions, the stacked gate unit, and the substrate, and a source electrode and a drain electrode, each located on the upper surface of the insulating layer and extending therethrough to make electrical contact with their respective junction regions, and a gate electrode located on the upper surface of said insulating layer and extending therethrough to make electrical contact with the upper metal layer of the stacked gate unit.